Dc/dc convertor power module package incorporating a stacked controller and construction methodology

ABSTRACT

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

TECHNICAL FIELD

The present invention relates generally to power converter devices usedin association with semiconductor systems. In particular, the inventionrefers to power converters used in DC-DC power level shifting devicesand associated packages having reduced sizes and footprints. Also, theinvention relates to methods of construction and packaging of thesereduced size converter packages.

BACKGROUND OF THE INVENTION

In the field of electronic and computer devices, there is a need forconverting one power level to another power level to enable theoperation of various systems. The power level required for the variouselectronic systems is quite commonly different from a power levelprovided to the electronic device. Also, several different power levelsmay be required to power the various systems of an electronic device.

Also, the same electronic device typically includes systems requiringseveral different power levels. Thus, in many electronic devices, thereis a need for one or more power level shifters.

Power level shifters generally include a power module (also referred toherein as a power converter) and several associated systems (inductor's,capacitors, and the like). Power level shifters can consist of FieldEffect Transistors (FETs) and controller ICs. One such arrangement isshown in FIG. 1( a)

In the depicted prior art convertor 10 a low side field effecttransistor (LS FET) 11 is arranged on a lead frame 12. Also, a high sidefield effect transistor (HS FET) 13 and an associated controller 14arranged on the lead frame 12. A pair of conductive clips (C1, C2)conductively interconnect the HS FET with the LS FET to form a switchingconnection. A problem with this arrangement is that the pair of clipsare required to appropriately connect the LS FET 11, the HS FET 13, andthe controller 14. A fair amount of time and effort is required toposition, align, and attach and otherwise connect the clips (C1, C2)with the FET's of the package 10. Thus, the number of components and thealignment difficulties associated with them results in increasedfabrication costs and higher failure rates in the packages produced.Additionally, the layout of FIG. 1( a) presents a relatively largesurface area due its planar die arrangement. This large surface area isbecoming increasingly problematic when faced with the decreasing size ofconsumer electronic devices. Accordingly, a need for devices (includingpower convertors) having a smaller “footprint” is desirable. Thedepicted prior art converter package 10 has a very large surface area.This takes up valuable real estate on various electronic substrates. Soboth the large footprint of prior art device and the need for two clipsare disadvantages of the prior art.

Accordingly, as explained in this patent, a power converter packagehaving a more compact structure with a reduced foot print, a simplifiedmanufacturing structure, and improved fabrication processes isdesirable. It is one of the objects of this patent to provide such apackage and modes for its manufacture.

SUMMARY OF THE INVENTION

In a first aspect, an embodiment of the invention describes powerconverter package having a high side (HS) field effect transistor (FET)mounted on a lead frame and a low side (LS) field effect transistor(FET) mounted on the same lead frame. A conductive clip can electricallycouple the two FET's. And a controller device is arranged above theconductive clip. One possible implementation is illustrated in theembodiment of FIG. 2( a). The HS FET and the LS FET are electricallyconnected with the HS FET and the LS FET to control the device. Furtheraspects can include the addition of a connector arranged to providepower to the various converter systems including the controller, HS FET,and the LS FET. Such packages can be encapsulated and singulated fromlarger arrays of such packages.

In another aspect, embodiments of the invention describe another powerconverter package. Such a package includes a low side field effecttransistor (LS FET) mounted on a lead frame and a controller mounted onthe same lead frame. A conductive clip is mounted on and electricallycoupled with the LS FET and a high side field effect transistor (HS FET)to establish a switch connection for the package. An interposer elementis arranged on the clip and between the HS FET and the clip to enablecurrent to pass from a drain of the LS FET to a source of the HS FET. Anaspect of the interposer element is to reorient the gate contact of theHS FET to face upward to form an improved wire bonding surface. Furtheraspects can include a power connector to provide power to the variousconverter systems. Such packages can be encapsulated and singulated fromlarger arrays of such packages.

In another aspect, embodiments of the invention describe a method forforming a power converter package. The method includes electricallycoupling a high side (HS) field effect transistor (FET) and a low side(LS) field effect transistor (FET) to die attach pads of a lead frame. Afirst side of clip is electrically coupled to a drain of the LS FET anda source of the HS FET to form a switch connection such that a portionof the clip is also electrically coupled with a switch node of the leadframe. A controller can be non-conductively coupled with a second sideof the clip. The gates of the HS FET and LS FET are electricallyconnected with the controller using wire bonding or other processes. Anelectrical connector can be added above the controller to provide powerto controller and other systems of the package. The power converterpackage is encapsulated and singulated to form a completed powerconverter package.

In another aspect, embodiments of the invention describe a method forforming another embodiment of the power converter package. The methodinvolves electrically coupling a LS FET to a die attach pad of a leadframe and non-conductively coupling a controller to the lead frame. Afirst side of a clip is electrically coupled with a drain of the LS FETand to a switch lead of the lead frame. An interposer element isarranged on a second side of the first clip opposite from the LS FET.The interposer element has a conductive gate tab and a conductivechannel. A HS FET is coupled with the interposer element such that asource of the HS FET is coupled with the channel. The connection of theHS FET source, interposer channel, LS drain, and the switch lead for aswitch connection. And the gate of the HS FET is coupled with the gatetab of the interposer. The controller is wire bonded to the HS FET gateusing the interposer gate tab. The controller is wire bonded to the LSgate through a lead of the lead frame. The package is encapsulated andsingulated to form converter packages.

General aspects of the invention include, but are not limited tomethods, systems, apparatus, and related products for enabling thefabrication of reduced form factor power converter packages and theinventive power converter packages themselves.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention and the advantages thereof may best be understood byreference to the following description taken in conjunction with theaccompanying drawings in which:

FIG. 1( a) is a plan view of a state of the art power converter deviceused level shifters

FIG. 1( b) is a simplified diagrammatic plan view of an embodiment ofpower converter device in accordance with the principles of the presentinvention.

FIG. 2( a) is a simplified side section view of a portion of a powerconverter apparatus with a controller stacked above the FET device inaccordance with the principles of embodiment of the present invention.

FIG. 2( b) is a simplified flow diagram illustrating a processembodiment enabling the construction of power converter devices having acontroller stacked above the FET device in accordance with theprinciples of embodiment of the present invention.

FIG. 3 is a simplified side section view of a portion of a powerconverter apparatus with a HS FET stacked above a LS FET and includingan interposer element to reorient a gate connection in accordance withthe principles of embodiment of the present invention.

FIGS. 4( a)-4(j) are a set of drawings that illustrate a processembodiment that enables construction of a stacked FET power converterincluding an interposer element in accordance with the principles ofembodiment of the present invention.

FIG. 5 is a flow diagram that illustrates a process embodiment thatenabling construction of a stacked FET power converter including aninterposer element in accordance with the principles of embodiment ofthe present invention.

In the drawings, like reference numerals are sometimes used to designatelike structural elements. It should also be appreciated that thedepictions in the figures are diagrammatic and not to scale.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Reference is made to particular embodiments of the invention. Examplesof which are illustrated in the accompanying drawings. While theinvention will be described in conjunction with particular embodiments,it will be understood that it is not intended to limit the invention tothe described embodiments. To contrary, the disclosure is intended toextend to cover alternatives, modifications, and equivalents as may beincluded within the spirit and scope of the invention as defined by theappended claims.

Aspects of the invention pertain to novel power converter modules ordevices used in power level shifting applications and the methods offabricating and packaging such devices. Such power converters are usedin DC-DC voltage level shifting devices. For example in DC-DC step downlevel shifters and the like. In one example, a synchronous buck topologycan be used in power converter modules used, for example, in a DC-DCpower level shifter. Aims of the inventive technologies are to reducepower converter module footprint (surface area), increase power density(current per unit area), and simplify manufacturing by reducing thepresently used two clip structure to one clip.

In another aspect, in a “stacked FET” implementation, the controllerrests on the leadframe die attach pad (DAP). This orientation in groundsthe controller thereby substantially immunizing it from noise generatedby the operation of the FET's. Additionally, this arrangementfacilitates the possibility of having vias in a multi layer PCB forimproved heat dissipation. Accordingly, this implementation has certainadvantages when applied to PCB layouts.

In the diagrammatic illustration of FIG. 1( b), an embodiment of aninventive power converter module is shown and shall now be described.The power converter device 100 includes a substrate 103 upon which someof the power converter module systems and devices are arranged. Thesubstrate 103 can include a lead frame 103 having die attach pads and aplurality of conductive leads. The lead frame 103 can comprise one ofmany such lead frames arranged in a lead frame array. Of course othersuitable substrates may also be used.

To continue, rather than arranging all of the systems (11, 13, 14 asshown in FIG. 1( a)) on a common level as in the prior art, theinventors employ propose a multi-level structure to form a more compactpackage. The following Figures and disclosure address this issue.

In the simplified description of FIG. 1( b), the package 100 comprises asubstrate 103 upon which other systems and components are arranged. Insome embodiments, the substrate 103 comprises a lead frame which can bea pre-molded lead frame. Such a pre-molded lead frame is merely apartially fabricated lead frame. Such a pre-molded lead frame portionsof the lead frame are treated with encapsulant materials lendingrigidity to the pre-molded lead frame. More commonly, a standard leadframe (one having no encapsulant used) can be used. In general, the leadframe 103 includes one or more conductive die attach pads (e.g., 101 d,102 d) and a plurality of conductive leads arranged peripherally aboutthe substrate 103.

In one embodiment, a HS FET 101 and a LS FET 102 can be arranged on thedie attach pads (101 d, 102 d) of the substrate 103. Also, a clip (notshown in this view) electrically couple the HS FET 101 with the LS FET102. A more detailed explanation of the clip connections will bediscussed below. Briefly, the clip 109 is arranged above, and connectedwith, both the HS FET 101 and the LS FET 102. A controller device 106 isnon-conductively mounted on the clip 109. The controller 106 is operableto selectively activate/deactivate and otherwise control the operationof the two FET's (101, 102). A structure this compact substantiallydecreases the footprint of the package. This embodiment can reduce thefootprint of this power converter package by 30-50% relative to anordinary prior art converter module. Much of the size reduction isachieved by moving the controller 106 onto a different level of thedevice that the FET's.

FIG. 2( a) illustrates a side cross section view of a portion of oneparticular embodiment of a converter package 200. To begin the packageincludes a substrate that comprises a lead frame 203 having two dieattach pads (DAP's) 211, 212 arranged to mount and electrically connectwith the HS FET 201 and the LS FET 202 and also a clip 209 and acontroller 206.

The first pad (DAP 211) is electrically coupled with the HS FET 201. TheHS FET 201 has a bottom surface having a drain contact 201D and also afacing surface having a source contact 201S and a gate contact 201S. Thesource 201S and gate 201G are arranged on a facing surface of the HS FET201 and the drain 202D is arranged on a bottom surface of the HS FET201. The HS FET is mounted “face up” such that the drain 201D isarranged on the first DAP 211.

The second DAP 212 is electrically coupled with the LS FET 202. Like HSFET 201, the LS FET 202 has a bottom surface having a drain contact 202Dand also a facing surface having a source contact 202S and a gatecontact 202S. The source 202S and gate 202G are arranged on a facingsurface of the LS FET 202 and the drain 202D is arranged on a bottomsurface of the LS FET 202. The LS FET 202 is mounted “face down” suchthat the source 202S is arranged on the second DAP 212. And also, the LSgate 202G is electrically coupled with the lead 213 of lead frame 203.The lead 213 can extend under the LS FET 202 to enable connection withLS gate 202G.

In one implementation, the FET's themselves can be attached using asolder paste or, alternatively ball grid array (BGA) type connectionscan be used. A reflow process can be used to affix and electricallyconnect the HS FET 201 and LS FET 202 onto the DAP's 211 and 212respectively. It is to be pointed out that beyond the disclosed solderpaste and BGA implementations, other methods known to persons ofordinary skill in the art can be used to accomplish the same task. Thisconfiguration can be extended to at least some of the other FETconnections as well.

A conductive clip 209 is mounted on and electrically connected with theFET's 201, 202 and contact leads of the lead frame 203. In particular,the clip 209 electrically connects the HS FET source 201S with the LSFET drain 202D and also with switch pins of the lead frame, defined hereby contact 215 of the lead frame 203, to establish a switch pins for thepackage 200.

The lead frame 203, the two FET's 201, 202, and the clip 209 can beassembled and then affixed using a single reflow process if desired.This assembly (201, 202, 203, and 209) can be referred to as a leadframe sub-assembly.

Advantageously, a controller 206 is then mounted on an opposing side ofthe clip 209. Adhesives and epoxies can be used. In one implementation,the controller 206 can be mounted with the clip 209 using an epoxy, forexample, in one implementation, non-conductive epoxies or othernon-conductive adhesive can be used.

The controller 206 is wire bonded to the gate contact 201G of the HS FET201, for example, using wire bond 207 a. The wire bond 207 a willelectrically connect with the gate 202G through an opening 211 or cutout portion of the clip 209. Also, the controller 206 is wire bonded 207b with gate 202G. In most implementations this will mean wire bonding toan exposed portion of a lead 213 that is electrically coupled with thegate 202G.

These gate connections (e.g., the 207 a, 207 b to the gates 201G, 202G)enable the controller 206 to control the operation of the FET's 201,202. Additionally, power can be supplied to the controller 206 using apower connection (not shown) which can, for example, be connected withleads of the lead frame assigned for that purpose.

As a general note, because the LS FET 202 is arranged face down, thelead that 213 couples with the gate 202G also should include a portionthat extends beyond an outer periphery of the LS FET 202 to provide agood exposed bonding surface for the wire bond 207 b.

Additional wire bonds (not shown in this view) are also formedconnecting the controller 206 to various leads of the lead frame 203.This structure is then encapsulated, using an epoxy or other encapsulantmaterial. Commonly such converter packages 200 are assembled in an arrayformat and accordingly are singulated to form individual powerconverters 200.

FIG. 2( b) is a flow diagram that can be used to illustrate an exampleprocess embodiment used to form such power converters. A process canbegin by providing a lead frame substrate 203 (Step 221). This can be awafer scale array of lead frames arranged for fabrication. Additionally,a pre-molded array of lead frames can be used. Such a pre-molded leadframe is merely a lead frame treated with an encapsulant (or othermaterial) to lend structural rigidity. It should also be pointed outthat in other implementations, power convertor can be formed withoutusing said pre-molded lead frames.

This lead frame 203 can then be treated with a solder paste to formsuitable bonding sites on the leadframe 203 (Step 223). In one commonimplementation, the solder paste is stenciled or otherwise arranged inplace on the lead frame 203. The various mounting sites of a lead framearray are treated with the paste preparing them for FET attachment. Forexample, solder paste layers are placed on DAP's 211 and 212 and bondingsite 213 associated with the LS gate contact 202G. It is also noted thatalternatively, or additionally, the FET's (201, 202) can be treated withsolder paste or to place in readiness for bonding to the lead frame 203.Any of a number of solder paste processes can be used.

The FET's (201,202) are appropriately attached to the solder paste sitesindicated above (Step 225).

A clip 209 is treated with solder paste (Step 227). Accordingly, asolder paste is also attached to a clip 209 in a manner suitable forfacilitating the attachment of the FET's (201, 202) with the clip 209and also to further facilitate the mounting of the lead frame 203 (at215) with the clip 209. Also, in some embodiments, the solder paste canbe applied to the FET's (201, 202) and lead frame (at 215) instead ofthe clip.

The clip 209 is mounted with the FET's (201, 202) and the leadframe 203(Step 229) to form a lead frame, clip and FET subassembly.

This subassembly is then subject to a reflow process (Step 231) toelectrically connect together the FET's (201, 202), the clip 209, andthe lead frame 203. In one example, a reflow process lasting for aboutthree to four minutes having a peak temperature of in the range of about260° to about 360° is suitable. It is however pointed out that otherreflow parameters and materials can be used in accordance with theprinciples of the invention.

It should be pointed out that the prior operation can be performed in anorder that is subject to some variation. In a preferred embodiment, thepre-reflow steps (Steps 221-229) should be performed before the reflowoperation (Step 231) however several reflow operations can be used.

Subsequently, in one preferred embodiment, the controller 206 is thenmounted on the clip 209 (Step 233). In one example, the controller 206can simply be adhered to the clip 209 using an adhesive which can be caninclude conductive and non-conductive adhesives as well as others. Manytypes of epoxies work well for such implementations. Some examplesinclude, but are not limited to Ablestik 8387 and QMI 536 HT. as well asothers.

It is worth point out that the operations discussed with respect to229-233 can be performed in a slightly different manner. The controller206 can be mounted on one side of the clip. Then the clip is flippedover and the HS FET 201 and the LS FET 202 are coupled to a second sideof the clip in a “flip chip” type attachment scheme. This assembly isthen mounted with the lead frame 203.

Once mounted, the controller 206 is attached to the systems of thepackage using wire bonds (207, etc.) (Step 235). Such as indicated abovein FIG. 2( a). Typically a number of other leads of the lead frame 203are wire bonded with, or otherwise connected with the controller 206.Such can include power and ground contacts as well as system inputs tothe controller 206.

The completed device package is then encapsulated using an appropriateencapsulant (Step 237). One example of such an encapsulant is CEL 9220.Others can also be used.

Once the encapsulant is cured, an array of formed and encapsulatedconverter packages can be singulated into separate device packages (Step239).

Such an implementation carries with it the advantages of reducing thenumber of DAP's from three to two and reduces the number of clips fromprior art two clips to the disclosed implementation having only one.This results in reduced manufacturing overhead and therefore reducedcost.

The diagrammatic illustration of FIG. 3 highlights another approachusing a stacked FET design that is enhanced by the presence of aninterposer element. In this embodiment the power converter 300 includesa substrate 303 upon which power converter systems and devices arearranged. The substrate 303 can include die attach pads (e.g. 311) andconductive leads arranged about the periphery of the substrate. In oneimplementation, the substrate 303 comprises a lead frame. On a waferscale, the lead frame can comprise one of many such lead frames arrangedin a lead frame array. Other suitable substrates may also be used.

The simplified illustration of FIG. 3 shows a side sectional view ofportions of the multi-level converter package 300 embodiment. To createa smaller footprint, this embodiment stacks the HS and LS FET's (201,202) generally one over the other and employs an offset controller 206mounted with the lead frame 303. Accordingly, it is a stackedarrangement of a different type than illustrated in FIG. 1( a).

To begin, the lead frame 303 comprises a die attach pad (DAP) 311 and aplurality of leads including, but not limited to leads 313 and 316 (someothers are described elsewhere in this patent).

A LS FET 202 is mounted on the lead frame 303. Such a FET can be mounted“face down”, that is the face surface gate contact 202G and sourcecontact 202S are facing toward the lead frame 303. In particular, thesource 202S is electrically contacted with the DAP 311. Also, the gate202G is electrically contacted with a gate lead 313. Thus, in oneembodiment, the lead 313 is configured such that when the LS FET 202 ismounted on the lead frame 303, the lead 313 extends under the LS FET 202to enable electrical connection between lead 313 and LS FET gate 202G.

To continue, the DAP 311 and gate lead contact 313 typically use solderpaste in areas area 313 s and 311 s to attach the LS FET 202 to the leadframe 303. As before, these connections can be made using solder paste(as shown here) or BGA type connections. A reflow process can be used toaffix and electrically connect the LS FET 202 with the lead frame 303.

Also, a clip 309 is mounted with the package 300. Typically, the clip309 is electrically connected with the drain 202D of the LS FET 202. Theclip 309 is also electrically connected with a lead 318 of the leadframe 303. The lead 318 comprises a switch node pin 318 for the package300. Also the clip 309 is connected with a source 201S of the LS FET201. It should be pointed out that the nature of this connecting isexplained in fuller detail elsewhere in the patent. To continue thecombination of electrical connections between the switch node 318, theclip 309, the LS FET drain 202D, and the HS FET source 201S defines aswitch connection for the package 300.

On the other side of the clip 309 is arranged an interposer element 321.A typical interposer element 321 has a non-conductive core withelectrical connections formed therein. The core can be formed ofdielectric materials and insulating materials. The interposer element321 includes a conductive channel 332 and a gate tab 323. The channel322 is a conductive channel that passes through the interposer 321 tocreate a conduction path. The gate conductive tab 323 is formed tointerface with a HS FET gate contact 201G. The tab 323 typically doesnot extend all the way through the interposer 321. This generallyprevents shorting against the clip 309 when mounted. Generally, thechannel 322 and gate tab 323 comprise conductive materials (like silver,aluminum, gold, as well as many others).

In operation the interposer 321 is generally mated with the HS FET 201to form a subassembly that can be mounted onto the clip 309 as a unit.In this case, the HS FET 201 is mounted to the interposer 321 in a “facedown” orientation. That is to say that the facing surface (that includessource 201S and gate 201G contacts) is arranged so that it faces theinterposer element 321. Typically, a solder paste is applied between theHS gate 201G and the tab 323 and also between the HS source 201S and thechannel 322 and the whole is reflowed to form the subassembly. However,there are implementations where the interposer 321 is coupled with theclip 309 first, and then the HS FET 201 is attached later.

To continue, the channel 322 of the interposer 321 is intended tofacilitate conductive connection between the source 201S and the clip309 which in turn is coupled with the LS drain 202D forming the switchconnection.

Additionally, the gate tab 323 is configured to enable reorientation ofa HS gate contact 201G so that it presents an improved wire bondingsurface (such as 324). Accordingly, the gate tab 323 is arranged toelectrically couple with the HS gate connection 201G. This arrangementtransforms a relatively poor bonding surface 201G into a good wirebonding surface 324 on a top surface of tab 323. Thus, the gate tab 323is sized and shaped so it will extend beyond the outer periphery of theHS FET 201. In general, the exposed portion 324 of the gate tab 323 onlyneed be big enough to provide a sufficient wire bonding surface. Asalready indicated, the conductive tab 323 typically does not extend allthe way through the interposer. Accordingly, the gate and drain of theHS-FET are arranged on the same side of the die

Accordingly, one surface of the interposer element 321 is mounted on theclip 309 while the other has the HS FET 201 mounted thereto.

Thus, in the package 300, the conductive channel 322 of the interposerelement 321 is electrically connected with the HS FET source 2015 andwith the clip 309. And the tab 323 is electrically connected with the HSFET gate 201G.

Solder paste can be used to facilitate the connections betweeninterposer 321 and the clip 309. Once attached to the clip, a reflowprocess can again be performed.

Also, a controller 206 is coupled with the lead frame 303 rather thanstacked above the FET's, as in the previous embodiment. The controller206 can be attached to the lead frame using an epoxy which can be caninclude conductive and non-conductive adhesives as well as others. Thecontroller 206 is then wire bonded 307 b to a lead 313 to establishelectrical connect with the LS FET gate contact 202G. And the controller206 is also wire bonded 307 a to a gate tab 323 of an interposer element321 to couple with the gate 202G of the LS FET 202.

Advantageous aspects of this configuration are that it reduces footprint and that by using the interposer element 321 certain difficultiesin the prior art are eliminated while retaining many of its bestfeatures.

It is pointed out that electrical connections like Vin and other powerconnections can be appropriately routed and connected with the FET's andcontroller. This structure is then encapsulated. Typically using anepoxy or other encapsulating material. Commonly such converter packagesare assembled on a wafer scale. Accordingly, the individual packages canbe formed by singulating such wafers into individual power converters.

FIGS. 4( a)-4(j) and FIG. 5 provide a series of fabrication operationsused in an example process for fabricating power convertors such asdiscussed with respect to FIG. 3. A process can begin by providing alead frame substrate 303 and preparing it for further fabrication (Step501). Commonly this will be a wafer scale array of such lead frames.Such an array can comprise wafer scale plurality of lead frames arrangedfor fabrication. Additionally, a pre-molded array of lead frames can beused. For example, a lead frame 303 can be treated with encapsulant (orother material) to lend structural rigidity, if desired. The simplifiedillustration of FIG. 4( a) illustrates a lead frame embodiment 303. Sucha lead frame 303 can be configured in a number of different formats. Inthe depicted embodiment a single DAP 311 can be used along with a numberof leads (e.g., 313, 315, 318 and a general arrangement of various otherleads 317). Additionally, the lead frame 303 can then be treated with asolder paste to form suitable bonding sites 311 s, 313 s for electricalconnections between contacts and components to be mounted the lead frame303. For example, a solder pad 311 s is arranged to connect with asource 202G of the LS FET. A gate solder pad 313 s is arranged toconnect a LS FET gate 202G with lead 313. Formation of such solder pads313 s, 311 s can be achieved using a variety of methods known in theart.

FIG. 4( b) illustrates an example of the positioning, aligning, andmoving 531 of the LS FET 202 into attachment with the solder pads 311 s,313 s. The LS FET 202 is then positioned 531 and attached to the solderpaste sites (313 s, 311 s) (Step 503). This attachment is typicallyfacilitated with a reflow process. Additionally, alternate embodimentsemploy a BGA attachment process rather than the solder paste method.

As shown in the simplified diagram of FIG. 4( c), the bottom surface(that is to say, the upward facing drain contact) of the LS FET 202 istreated with solder paste 532 to present a suitable bonding surface(Step 505). Alternatively, a portion of a subsequently mounted clip 309can alternatively be treated with a solder paste and then subsequentlymounted with the HS FET 202.

As shown in the simplified diagram of FIG. 4( d), the clip 309 ismounted in contact with the layer of solder paste 532 (i.e., drain 202Dof the LS FET) (Step 507). Additionally, the clip 309 is electricallycoupled with a switch node 315 of lead frame 303. This can also besubject to reflow.

As shown in FIG. 4( e) a method of forming an interposer-FETsub-assembly 533 is shown (See, also FIG. 4( f) below). Such asub-assembly is formed by coupling the HS FET 201 with the interposerelement 321 (Step 509). The interposer element 321 having a conductivechannel 322 and a gate connection tab 323. As indicated above, theconductive channel 322 is configured to enable a current path throughthe interposer element 321. Typically this path describe current flowsbetween the HS FET source 201S and the clip 309. Also, the gateconnection tab 323 is configured such that it provides good electricalconnection with a HS FET gate 201G and so that extends beyond an outerperiphery of the HS FET 201 to present a good accessible bonding surface324. In this view the conductive channel 322 and gate connection tab 323are shown. As are the gate 201G and the source 201S contacts of the HSFET 201. In this implementation the HS FET 201 is mounted on theinterposer element 321 to form the interposer-FET subassembly 533 (See,e.g., FIG. 4( f)).

As shown in FIG. 4( f) the interposer-FET subassembly 533 is thenmounted with the clip 309 (Step 511). In one example approach, a solderpaste layer 534 is formed on the clip 309 and the interposer-FETsubassembly 533 is mounted with the clip 309. The mounting enabling theelectrical communication between the conductive channel 322 and the HSFET source 201S and between the clip 309, for example, using the layer534. Additionally, and importantly the gate tab 323 is exposed for wirebonding. Such is reflowed to facilitate the connection betweensubassembly 533 and clip 309.

It should be pointed out that in other approaches for mounting theinterposer element 321 can include mounting the interposer separatelywith the clip 309 and then adding the HS FET 201.

As shown in FIG. 4( g), an electrical power connector 535 can be mountedwith the package to electrically couple the power connector 535 with theHS FET 201 (Step 513). The power connector 535 is mounted so as to notobscure the bonding surface 324 of the interposer gate tab 323. Itshould be pointed out that this connection between the HS FET 201 andthe connector 535 can be facilitated using a layer of solder paste 536arranged on a drain contact 201D of the HS FET 201. Also, the powerconnector 535 can be connected with one of the leads 318 of the leadframe 303 to enable connection with an external power source.Accordingly, the connection of a lead 318 with the connector 535 canprovide power (such as Vin) to the HS FET 201. Accordingly, by moving537 the connector 535 into position establishes an electrical connectionbetween an external power source, the lead 318, and the HS FET 201, forexample, as indicated in FIG. 4( h). The structure can then be reflowed.As mentioned above, instead of a solder paste a BGA type connection canbe employed.

If desired all of the preceding reflow processes can be formed at thisstage, before the addition of the controller. Moreover, the controllercan be solderable. Thus, enabling the controller can be attached at thesame time as the LS FET.

FIG. 4( h) illustrates a process where the connector 206 is attached tothe lead frame 303 (Step 515). Commonly, the controller 206 isnon-conductively mounted on the lead frame 303. For example, thecontroller 206 can simply be adhered to the lead frame 303 using anadhesive 537.

FIG. 4( i) illustrates a process where the connector 206 is wire bondedto various package systems and contacts (Step 517). Once mounted, thecontroller 206 is attached to the systems of the package using variouswire bonds 307. For example, the controller is wire bonded 307 b with LSFET gate 202G (in this case using contact lead 313). Also, a wire bond307 a connects the controller 206 with HS FET gate 201G (i.e., throughthe gate tab 323 of the interposer 321). And also to various other leadsof the lead frame 203 are connected with the controller 206 using otherwire bonds 307. Such can include power and ground contacts as well assystem inputs to the controller 206.

The completed device package is then encapsulated using an appropriateencapsulant (Step 519). Once the encapsulant is cured, an array offormed and encapsulated converter packages can be singulated intoseparate device packages (Step 521). An embodiment of an encapsulatedand singulated package 400 is depicted in FIG. 4( j). In this view thebottom of the package is revealed. The bottom surface reveals theexposed bottom of the DAP 311. Also shown are a number of leads 317 aswell as leads 315 and 318. A portion of the lead 313 associated with theLS FET gate 202G is also exposed.

The foregoing description, for purposes of explanation, used specificnomenclature to provide a thorough understanding of the invention.However, it will be apparent to one skilled in the art that the specificdetails are not required in order to practice the invention. Thus, theforegoing descriptions of specific embodiments of the present inventionare presented for purposes of illustration and description. They are notintended to be exhaustive or to limit the invention to the precise formsdisclosed. It will be apparent to one of ordinary skill in the art thatmany modifications and variations are possible in view of the aboveteachings.

The embodiments were chosen and described in order to best explain theprinciples of the invention and its practical applications, to therebyenable others skilled in the art to best utilize the invention andvarious embodiments with various modifications as are suited to theparticular use contemplated. It is intended that the scope of theinvention be defined by the following claims and their equivalents.

1. A power converter package comprising, a lead frame having a first dieattach pad, a second die attach pad, and a plurality of leads includinga switch node that comprise at least one of the plurality of leads; ahigh side (HS) field effect transistor (FET), the HS FET includes asource contact and gate contact arranged on a face surface of the HS FETand a drain contact on a bottom surface of the HS FET and the bottomsurface of HS FET is mounted facing toward the lead frame and the drainof the HS FET is coupled with the first die attach pad; a low side (LS)field effect transistor (FET), the LS FET includes a source contact andgate contact arranged on a face surface of the LS FET and a draincontact on a bottom surface of the LS FET and the facing surface of LSFET is mounted facing toward the lead frame with the source of the LSFET coupled with the second die attach pad; an electrically conductiveclip that electrically connects with the source of the HS FET and thedrain of the LS FET and a lead frame switch node, wherein the switchnode comprises at least one of the plurality of leads of the lead frame,thereby defining a switch connection for the power converter package atleast one of the leads to form a switch connection, wherein theelectrically conductive clip electrically connects the HS FET and the LSFET using a bottom surface of the of the electrically conductive clip;and a controller device mounted with the clip and arranged above the HSFET and the LS FET and electrically connected with the HS FET and the LSFET.
 2. (canceled)
 3. The power converter package recited in claim 1,wherein the electrically conductive clip electrically connects thesource of the HS FET and the drain of the LS FET to establish anelectrical connection between the HS FET and the LS FET and said switchnode to form the switch connection.
 4. The power converter packagerecited in claim 3, wherein the controller is nonconductively mounted onthe second surface of the electrically conductive clip and wherein thecontroller is electrically connected with the gate contacts of the HSFET and the LS FET.
 5. The power converter package recited in claim 4,wherein the controller is electrically connected with the gate contactof the HS FET with a wire bond; and the controller is electricallyconnected with the gate contact of the LS FET with a wire bond.
 6. Apower converter package comprising, a lead frame having a die attach padand a plurality of leads; a low side field effect transistor (LS FET)comprising a gate contact and a source contact arranged on a facingsurface of the LS FET and a drain contact on a bottom surface of the LSFET, the LS FET further arranged on the die attach pad such that thesource contact of the LS FET is electrically coupled with the first dieattach pad such that the LS FET gate contact is electrically coupledwith at least one of said plurality of leads; a conductive clip arrangedabove the LS FET to enable electrical connection between a drain contactof the LS FET and the clip; an interposer element arranged on the clipand configured to reorient gate contacts of high side field effecttransistor (HS FET) mounted thereon; the HS FET is arranged on the clipsuch that an electrical contact passes through a conductive channel ofthe interposer enabling a current path between the HS FET source and theclip and such that a gate tab of the interposer connects with a gate ofthe HS FET wherein the gate tab presents a good wire bonding surface;and a controller mounted on the lead frame proximal to the LS FET andelectrically connected with the HS FET and the LS FET.
 7. The powerconverter package recited in claim 6, wherein the HS FET includes asource contact and gate contact arranged on a facing surface of the HSFET and a drain contact on a bottom surface of the HS FET; wherein theclip has a first surface and an opposing second surface; wherein theinterposer element is arranged on the first surface of the clip; the LSFET is arranged on the second surface of the clip; wherein the HS FETfacing surface is oriented toward the interposer enabling the interposerto reorient the gate contacts of HS FET to be exposed from abovepresenting suitable wire bonding surface; and wherein the channel of theinterposer enables the HS FET source contact to electrically connectwith the clip and therethrough connect with the drain contact of the LSFET to form a switch connection between the LS FET and the HS FET. 8.The power converter package recited in claim 7 wherein, the conductivetab of interposer element is formed on upper portion of the interposerelement does not penetrate all the way through the interposer element.9. The power converter package recited in claim 8 wherein, theconductive gate tab of the interposer element is electrically coupledwith the gate contact of the HS FET and extends beyond an outerperiphery of the HS FET to expose a top surface of the gate tab forminga gate bond pad for the HS FET.
 10. The power converter package recitedin claim 9 wherein, the controller is wired bonded to the HS FET usingthe gate tab of the interposer element.
 11. A method of forming a powerconverter package, the method comprising, electrically coupling a HS PETand a LS PET to die attach pads of a lead frame; electrically coupling afirst side of a conductive clip to a drain of the LS PET and a source ofthe HS PET to form a switch connection such that a portion of the clipis also electrically coupled with a switch node of the lead frame;non-conductively coupling a controller with a second side of the clip;wire bonding the connecting gates of the HS PET and LS PET with thecontroller; encapsulating the power converter package; and singulatingthe encapsulated package to form a completed power converter package.12. The method of claim 11 further including mounting a power connectorsuch that it is electrically coupled with a Vin node of the lead frameand is arranged to provide power the power converter package.
 13. Themethod of claim 11 wherein said coupling the first side of the firstclip to a drain of the LS PET and non-conductively coupling thecontroller with a second side of the first clip includes a flip chiptype process wherein a first one of the LS PET and the controller iscoupled with the clip which is then flipped over and then another one ofthe LS PET and the controller is coupled with the first clip.
 14. Themethod of claim 11 wherein said coupling of the LS PET and the HS PET tothe lead frame is conducted prior to the attachment of the clip.
 15. Themethod of claim 14 wherein said lead frame comprises a preformed leadframe.
 16. A method of forming a power converter package, the methodcomprising, electrically coupling a LS PET to a die attach pad of a leadframe; non-conductively coupling a controller to the lead frame;electrically coupling a first side of a clip to a drain of the LS FETand to a switch node of the lead frame; arranging an interposer elementon a second side of the clip, the interposer element having a gate taband a conductive channel that passes through the interposer element thatis electrically coupled with the drain of the LS FET; arranging a HS FETon the interposer such that a source of the HS FET is electricallycoupled with the drain of the LS FET through the channel such that theHS FET source, the HS FET drain, and the switch node are electricallycoupled via the clip to form a switch connection; wherein said arrangingof the HS FET on the interposer further includes arranging the HS FETsuch that HS FET gate is electrically coupled with the gate tab suchthat the gate tab extends beyond an outer periphery of the HS FET topresent a gate bonding surface; electrically connecting gates of the HSFET and LS FET with the controller using at least wire bonding to thecontroller; encapsulating the power converter package; and singulatingthe encapsulated package to form a completed power converter package.17. The method of claim 16 further including mounting a power connectorsuch that it is electrically coupled with a Vin node of the lead frameand is arranged to provide power to converter package.
 18. The method ofclaim 16 wherein said coupling of the LS FET and the controller to thelead frame is conducted prior to the attachment of the first clip. 19.The method of claim 16 wherein said lead frame comprises a preformedlead frame.
 20. The method of claim 16 wherein arranging said HS FET onthe interposer element comprises attaching the HS FET to the interposerelement to form an interposer sub-assembly which is mounted with theclip as a unit.
 21. The method of claim 20 wherein, the LS PET, the leadframe, and the first clip are assembled to form a lead framesub-assembly; the lead frame sub-assembly is coupled with the interposersub-assembly.
 22. The method of claim 16 wherein a power connector ismounted and arranged above the HS PET and electrically coupled with aYin lead of the lead frame and is electrically coupled with at least theHS PET.
 23. An interposer apparatus for use with a field effecttransistor (PET) device, the apparatus comprising, an interposer bodyhaving a first surface and a second surface with an interposer coresandwiched between the first surface and the second surface; aconductive channel arranged such that it has a first conductive contacton the first surface of the body and a second conductive contact on thesecond surface of the body with a conduction path that passes throughthe core electrically connecting the first conductive contact withsecond conductive contact; an electrical gate tab with an electricalcontact surface at the first surface of the of the interposer; and theapparatus configured to enable coupling with a PET device so that whenmounted, a PET source electrically couples with the first conductivecontact of the conductive channel at the first surface of the interposerand so that the PET gate electrically couples with the gate tab at thefirst surface of the interposer, and wherein the gate tab extends beyondan outer periphery of the mounted PET so that a portion of the tab isexposed on the first surface of the interposer thereby enabling the wirebonding to a PET drain and the gate tab on a same side of theinterposer.